Vittoriano Muttillo

PhD student

Felix 1, Room DEWS lab

Vittoriano Muttillo received his Bachelor’s degree and Master's Degree (summa cum laude) in Computer Science Engineering, and his Ph.D. in Information and Communication Technologies (cum laude) from the University of L'Aquila. In 2014 he was a researcher at Centre of Excellence DEWS (Design Methodologies for Embedded controllers, Wireless interconnect and System-on-chip), working on development of middleware for FPGA's embedded multi-core architectures in the context of CRAFTERS (Constraint and Application driven Tailoring Framework for Embedded Real-time Systems) ARTEMIS-JU European Project.

Currently, he is a pot-doc research fellow in the area of Information and Communication Technologies (ICT) at the Department of Information Engineering, Computer Science and Mathematics (DISIM), University of L’Aquila. His research interests focus on Embedded Systems, with a particular emphasis on Electronic Design Automation and Model-Based System Level HW/SW Co-Design area. He works on the development of EDA tools, mainly oriented to properly manage Mixed-Criticality and Cyber-Physical application on heterogeneous multi/many-core platform.

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List of Publications (see also: dblp - Google Scholar - Linkedin - Scopus)

Journal papers

Di Felice, P.; Finocchio, L.; Leombruni, D.; Muttillo, V.: "A proposal to expand the community of users able to process historical rainfall data  by means of the today available open source libraries", In: CIT. Journal of Computing and Information Technology, Vol 22, No 2, pp. 85-103, 2014 [PDF]

Muttillo, V.; Valente, G.; Federici, F.; Pomante, L.; Faccio, M.; Tieri, C.; Ferri, S.: "A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling system", In: EURASIP Journal on Embedded Systems, Vol 2016, No 1, pp. 1-15, 2016 [PDF]

G. Valente, V. Muttillo, M. Muttillo, G. Barile, A. Leoni, W. Tiberti, L. Pomante, SPOF - Slave Powerlink on FPGA for Smart Sensors and Actuators Interfacing for Industry 4.0 Applications. Energies 2019, 12, 1633. [PDF]

L. Pomante, V. Muttillo, B. Krena, T. Vojnar, F. Veljkovic, P. Magnin, M. Matschnig, B. Fischer, J. Martinez, T. Gruber, “The AQUAS ECSEL Project - Aggregated Quality Assurance for Systems: Co-Engineering Inside and Across the Product LifeCycle”, Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), 2019. [PDF]

Conference papers

Muttillo, V.; Federici, F.; Pomante, L.; Valente, G.; Faccio, M.; Tieri, C.: "Enhancing a FPGA-Based SMP Embedded Platform with OpenMP Support and Unobtrusive System Monitor", In: Proceedings of Euromicro Conference on Digital System Design (DSD) - Work in Progress Session (Erwin Grosspietsch, Konrad Klöckner, eds.)SEA-Publications: SEA-SR-44, 2015

Moro, A., Federici, F., Valente, G., Pomante, L., Faccio, M., Muttillo, V.: "Hardware Performance Sniffers for Embedded Systems Profiling", In: Intelligent Solutions in Embedded Systems (WISES), 12th International Workshop on, pp. 29-34, 29-30 Oct. 2015 [PDF]

Valente, G., Muttillo, V., Pomante, L., Federici, F., Faccio, M., Moro, A., Ferri, S., Tieri, C.: "A Flexible Profiling Sub-System for Reconfigurable Logic Architectures", In: Parallel, Distributed, and Network-Based Processing (PDP), 24th Euromicro International Conference on , pp. 373-376, 17-19 Feb 2016 [PDF]

Faccio, M.; Federici, F.; Marini, G.; Muttillo, V.; Pomante, L.; Valente, G.: "Design and validation of multicore embedded systems under time-to-prototype and high-performance constraints", In: Research and Technologies for Society and Industry, Technologies for smarter societies (RTSI), 2nd Internal Forum on, 7-9 Sep. 2016