Vittoriano Muttillo

Post-doc

Coppito 1, Room DEWS lab
vittoriano.muttillo@univaq.it

Vittoriano Muttillo received his Bachelor’s degree and Master's Degree (summa cum laude) in Computer Science Engineering, and his Ph.D. in Information and Communication Technologies (cum laude) from the University of L'Aquila. In 2014 he was a researcher at Centre of Excellence DEWS (Design Methodologies for Embedded controllers, Wireless interconnect and System-on-chip), working on the development of middleware for FPGA's embedded multi-core architectures in CRAFTERS (Constraint and Application driven Tailoring Framework for Embedded Real-time Systems) ARTEMIS-JU European Project. Currently, he is a research fellow in the area of Information and Communication Technologies (ICT) at the Department of Information Engineering, Computer Science and Mathematics (DISIM), University of L’Aquila. His research interests focus on Embedded Systems, with a particular emphasis on Electronic Design Automation and Model-Based System-Level HW/SW Co-Design area. He works on the development of EDA tools, mainly oriented to properly manage Mixed-Criticality and Cyber-Physical applications on heterogeneous multi/many-core platforms.

No data avilable

List of Publications (see also: dblp - Google Scholar - Linkedin - Scopus)

Journal papers

Di Felice, P.; Finocchio, L.; Leombruni, D.; Muttillo, V.: "A proposal to expand the community of users able to process historical rainfall data by means of the today available open-source libraries", In: CIT. Journal of Computing and Information Technology, Vol 22, No 2, pp. 85-103, 2014 [PDF]

Muttillo, V.; Valente, G.; Federici, F.; Pomante, L.; Faccio, M.; Tieri, C.; Ferri, S.: "A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling system", In: EURASIP Journal on Embedded Systems, Vol 2016, No 1, pp. 1-15, 2016 [PDF]

G. Valente, V. Muttillo, M. Muttillo, G. Barile, A. Leoni, W. Tiberti, L. Pomante, SPOF - Slave Powerlink on FPGA for Smart Sensors and Actuators Interfacing for Industry 4.0 Applications. Energies 2019, 12, 1633. [PDF]

L. Pomante, V. Muttillo, B. Krena, T. Vojnar, F. Veljkovic, P. Magnin, M. Matschnig, B. Fischer, J. Martinez, T. Gruber, “The AQUAS ECSEL Project - Aggregated Quality Assurance for Systems: Co-Engineering Inside and Across the Product LifeCycle”, Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), 2019. [PDF]

Valente, G., Giammatteo, P., Muttillo, V., Pomante, L., Di Mascio, T., A lightweight, hardware-based support for isolation in mixed-criticality network-on-chip architectures, (2019) Advances in Science, Technology and Engineering Systems, 4 (4), pp. 561-573.

V. Muttillo, L. Tiberi, L. Pomante, P. Serri, Benchmarking Analysis and Characterization of Hypervisors for Space Multicore Systems, 2019, Journal of Aerospace Information Systems, 500-511, 16, 11

L. Pomante, V. Muttillo, M. Santic, P. Serri, SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems, Microprocessors and Microsystems, Volume 72, 2020

Conference papers

V. Muttillo, P. Giammatteo, G. Fiorilli, L. Pomante, An OpenMP Parallel Genetic Algorithm for Design Space Exploration of Heterogeneous Multiprocessor Embedded Systems, PARMA-DITAM 2020

V. Muttillo, G. Fiorilli, and T. Di Mascio. 2019. Tuning DSE for Heterogeneous Multi-Processor Embedded Systems by means of a Self-Equalized Weighted Sum Method. In Proceedings of the 10th and 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2019). ACM, New York, NY, USA, Article 1, 4 pages.

V. Muttillo, "J4CS: An Early-Stage Statement-Level Metric for Energy Consumption of Embedded SW," 2019 8th Mediterranean Conference on Embedded Computing (MECO), Budva, Montenegro, 2019, pp. 1-5.

V. Muttillo, L. Pomante, P. Balbastre, J. Simò, and A. Crespo, "HW/SW Co-Design Framework for Mixed-Criticality Embedded Systems Considering Xtratum-Based SW Partitions," 2019 22nd Euromicro Conference on Digital System Design (DSD), Kallithea, Greece, 2019, pp. 554-561.

Muttillo, V., Valente, G., Pomante, L., Design space exploration for mixed-criticality embedded systems considering hypervisor-based SW Partitions, (2018) Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018, pp. 740-744

Muttillo, V., Valente, G., Injecting hypervisor-based software partitions into Design Space Exploration activities considering mixed-criticality requirements, (2018) 2018 7th Mediterranean Conference on Embedded Computing, MECO 2018 - Including ECYPS 2018, Proceedings, pp. 1-5.

Ciambrone, D., Muttillo, V., Pomante, L., Valente, G., HEPSIM: An ESL HW/SW co-simulator/analysis tool for heterogeneous parallel embedded systems, (2018) 2018 7th Mediterranean Conference on Embedded Computing, MECO 2018 - Including ECYPS 2018, Proceedings, pp. 1-6.

Muttillo, V., Valente, G., Pomante, L., Criticality-aware design space exploration for mixed-criticality embedded systems, (2018) ICPE 2018 - Companion of the 2018 ACM/SPEC International Conference on Performance Engineering, 2018-January, pp. 45-46

Muttillo, V., Stoico, V., Valente, G., D’Antonio, F., Pomante, L., Salice, F., CC4CS: An off-the-shelf unifying statement-level performance metric for HW/SW technologies, (2018) ICPE 2018 - Companion of the 2018 ACM/SPEC International Conference on Performance Engineering, 2018-January, pp. 119-122.

Muttillo, V., Valente, G., Pomante, L., Criticality-driven design space exploration for mixed-criticality heterogeneous parallel embedded systems, (2018) ACM International Conference Proceeding Series, pp. 63-68.

Muttillo, V., Valente, G., Ciambrone, D., Stoico, V., Pomante, L., Hepsycode-RT: A real-time extension for an ESL HW/SW Co-design methodology, (2018) ACM International Conference Proceeding Series.

Valente, G., Rotondi, M., Muttillo, V., Time bands: A software approach for timing analysis on resource-constrained systems, (2017) ICPE 2017 - Proceedings of the 2017 ACM/SPEC International Conference on Performance Engineering, pp. 161-162.

Di Pompeo, D., Incerto, E., Muttillo, V., Pomante, L., Valente, G., An efficient performance-driven approach for HW/SW Co-design, (2017) ICPE 2017 - Proceedings of the 2017 ACM/SPEC International Conference on Performance Engineering, pp. 323-326.

Federici, F., Micozzi, M., Muttillo, V., Pomante, L., Valente, G., Simulation-Based Analysis of a Hardware Mechanism to Support Isolation in Mixed-Criticality Network on Chip, (2017) Proceedings - UKSim-AMSS 11th European Modelling Symposium on Computer Modelling and Simulation, EMS 2017, pp. 185-190.

Faccio, M.; Federici, F.; Marini, G.; Muttillo, V.; Pomante, L.; Valente, G.: "Design and validation of multicore embedded systems under time-to-prototype and high-performance constraints", In: Research and Technologies for Society and Industry, Technologies for smarter societies (RTSI), 2nd Internal Forum on, 7-9 Sep. 2016

Valente, G., Muttillo, V., Pomante, L., Federici, F., Faccio, M., Moro, A., Ferri, S., Tieri, C.: "A Flexible Profiling Sub-System for Reconfigurable Logic Architectures", In: Parallel, Distributed, and Network-Based Processing (PDP), 24th Euromicro International Conference on, pp. 373-376, 17-19 Feb 2016 [PDF]

Moro, A., Federici, F., Valente, G., Pomante, L., Faccio, M., Muttillo, V.: "Hardware Performance Sniffers for Embedded Systems Profiling", In: Intelligent Solutions in Embedded Systems (WISES), 12th International Workshop on, pp. 29-34, 29-30 Oct. 2015 [PDF]

Muttillo, V.; Federici, F.; Pomante, L.; Valente, G.; Faccio, M.; Tieri, C.: "Enhancing a FPGA-Based SMP Embedded Platform with OpenMP Support and Unobtrusive System Monitor", In: Proceedings of Euromicro Conference on Digital System Design (DSD) - Work in Progress Session (Erwin Grosspietsch, Konrad Klöckner, eds.)SEA-Publications: SEA-SR-44, 2015