PhD student

Giacomo Valente

https://orcid.org/0000-0002-0155-3788

Runtime monitoring systems; Reconfigurable technologies; Edge-computing;
ING-INF/05 - Sistemi di elaborazione delle informazioni

Curriculum   Scholar Research Gate

Research

1st accepted poster to DATE 2016 - University Booth!

Title: "AIPHS – AdaptIve Profiling Hardware Sub-system"

Abstract: Run-time monitoring systems on reconfigurable logic have the advantage that they can be customized with respect to specific applications: in the context of automated testing, this can lead to powerful scenarios. This demo presents a smart monitoring system by showing both a customization for stalls identification in a message passing scenario (based on four MicroBlaze that executes a bare-metal FFT application), and a customization for bus utilization monitoring in a symmetric multi-processing system scenario (based on four Leon3 running a custom Linux kernel). The whole development flow (and related prototypal EDA tools), that starts exploiting a library of elements to compose the desired hardware profiler, that leads to the introduction of such a profiler in the target architecture, and that allows profiling data collection and analysis will be shown. Moreover, a comparison among different functionalities will be illustrated. Both systems will be illustrated by using Zynq7000 SoC.

 

2nd accepted poster to DATE 2016 - University Booth!

Title: "A-LOOP"

Abstract: Isles of computational elements with different characteristics can be exploited for separate tasks with different non-functional requirements. This can drive to realization of smart System On Modules (SoM). In such a context, SoC with FPGA can be viewed as platforms useful to prototype these architectures.This demo shows a SoM prototype for aerospace applications developed on Zynq7000 SoC, composed of dual-core ARM Cortex A9 with Linux operating system (isle#1) able to interface with external data, and quad-core Leon3 with SMP Linux operating system (isle#2), able to execute parallel applications based on OpenMP library. These 2 computational isles share an external DDR memory, so that isle#1 can provide data and collect results from isle#2. Moreover, isle#1 is able to monitor performance of isle#2 without introducing software overhead (i.e. no SW instrumentation) by using a hardware profiling system. The whole system that executes a MANET localization algorithm will be presented.

 

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